The present application generally relates to semiconductor fabrication techniques and, more specifically, to self-aligned patterning methods for use in fabricating semiconductor integrated circuits.
Various types of multi-patterning photolithography techniques can be utilized to manufacture semiconductor integrated circuits. Such multi-patterning techniques include sidewall image transfer (SIT), self-aligned double patterning (SADP), and self-aligned quadruple patterning (SAQP) techniques, for example. The current SIT, SADP and SAQP methods utilize deposition and etch back processes to create uniform memorization and transfer elements. In particular, these techniques involve spacer patterning steps in which spacers are formed on the sidewalls of sacrificial features (e.g., sacrificial mandrels), wherein the sacrificial features are removed to leave a pattern of spacers which is used to etch features into an underlying layer at sub-lithographic dimensions. One type of SADP method, referred to as spacer-is-dielectric (SID), utilizes the spacers (not sacrificial mandrels) to define dielectric spaces between target features (e.g., metal lines), which is in contrast to other SADP methods in which the spacers define the conductive features (metallization) which requires an extra cut mask to cut the spacers which wrap around end portions of the mandrels to avoid forming conductive loops.
SID SADP techniques are commonly utilized in back-end-of-line (BEOL) process flows for fabricating a metallization level comprising an array of parallel metal lines with uniform widths (e.g., minimum width—1×) and spacing. However, in some metallization levels, wider wires (e.g., greater than 1×) are desired to implement power rails, clock nets, analog wires, etc. The insertion of wider wires (greater than minimum width 1×) can be supported in SADP with severe limitations. For example, in a SID SADP process flow, the spacer width is fixed, while mandrel and non-mandrel widths can be modulated to pattern wider wires. However, the insertion of wide wires in an array of uniform wide wires is limited to a pair of wide wires to align the mandrel/non-mandrel assignment. Furthermore, wider mandrel shapes also present a challenge to the lithography fidelity of adjacent 1×-width features.